Event-driven simulation

Eg. simulating a digital circuit (including gate delays), or simulating SNNs

The essential idea is to create stateful objects for wires or neurons that are in turn connected to other stateful objects through procedures (logic gates or synapses). The procedures monitor the input states, and register operations to be performed (changes in the output states) after any delays whenever the inputs change. The operations are registered in an agenda that is a timed list of operations to be done, organised as a list of queues (one queue per time step).